1. Field of the Invention
This invention relates to computer systems, and more particularly to a multiprocessor system having a mirrored-memory architecture.
2. Description of Related Art
Multi-processor systems in the past have been designed to share data in a common memory unit. Other multiprocessor systems have been designed to share data in several common memory units. However, such systems do not generally provide multiple memory units for purposes of fault tolerance if one memory unit fails. That is, the data in the multiple memory units is generally not redundant.
In some environments, such as real-time transaction processing, it is important to provide redundant elements throughout a computer system in order to prevent the failure of a single element from halting processing. A common technique for providing such redundancy is "mirroring", which is the provision of identical elements operating in parallel on the same data and command streams. Another method of providing such redundancy is the provision of error correction and detection circuitry in conjunction with using extra bits of error correction code information. This technique is commonly used in memory units, where the cost of providing duplicate memory units usually exceeds the cost of providing ECC bits and error correction and detection circuitry. However, in some environments, such redundancy does not provide adequate protection against massive failure of the memory unit itself.
In such circumstances, a need exists to provide redundant memory functionality through mirrored pairs of memory units. Whenever data is written to memory, both mirrored memory units receive and store the data. Thus, if one memory unit completely fails, the other memory unit is available to provide continuous processing.
In the past, such mirrored memory systems have used sequential updating of the memory units. That is, data is written first to one memory unit, then to the other memory unit, because such systems have been limited to communicating over a single bus. In some real-time processing systems, sequential updating is not fast enough to provide adequate response time to incoming commands and requests. Further, determining that two such sequentially updated memory units are in fact identical can be difficult and time consuming. Another difficulty posed by sequentially-updated memory units is "equalizing" a replacement unit in real-time from a surviving on-line unit without significant degradation in processing throughput.
Therefore, a need still exists for providing fast mirrored memory functionality in a multiprocessor design. The present invention provides a novel solution to this problem.